REDUCED INSTRUCTION SET COMPUTERS
Studies of the execution behavior of high-level language programs have provided guidance in designing a new type of processor architecture：the reduced instruction set computer（RISC）．Assignment statements predominate，suggesting that the simple movement of data should be optimized．There are also many IF and LOOP instructions，which suggest that the underlying sequence control mechanism needs to be optimized to permit efficient pipelining．Studies of operand reference patterns suggest that it should be possible to enhance performance by keeping a moderate number of operands in registers．
These studies have motivated the key characteristics of RISC machines：（1）a limited instruction set with a fixed format．（2）a large number of registers or the use of a compiler that optimizes register usage，and（3）an emphasis on optimizing the instruction pipeline．
The simple instruction set of a RISC lends itself to efficient pipelining because there are fewer and more predictable operations performed per instruction．[1] A RISC instruction set architecture also lends itself to the delayed branch technique，in which branch instructions are rearranged with other instructions to improve pipeline efficiency．
Although RISC systems have been defined and designed in a variety of ways by different groups，the key elements shared by most designs are these：
．A large number of general-purpose registers，or the use of compiler technology to optimize register usage
．A limited and simple instruction set
．An emphasis on optimizing the instruction pipeline
Table 2-1 compares several RISC and non-RISC systems.
1．Instruction Execution Characteristics
To understand the line of reasoning of the RISC advocates，we begin with a brief review of instruction execution characteristics．The aspects of computation of interest are as follows：
? Operations performed：These determine the functions to be performed by the processor and its interaction with memory．
? Operands used：The types of operands and the frequency of their use determine the memory organization for storing them and the addressing modes for accessing them．
? Execution sequencing：This determines the control and pipeline organization．
2．The Use of A Large Register File [2]
The reason that register storage is indicated is that it is the fastest available storage device，faster than both main memory and cache．The register file is physically small，generally on the same chip as the ALU and control unit，and employs much shorter addresses than addresses for cache and memory．Thus，a strategy is needed that will allow the most frequently accessed operands to be kept in registers and to minimize register-memory operations．
Two basic approaches are possible，one based on software and the other on hardware．The software approach is to rely on the compiler to maximize register usage．The compiler will attempt to allocate registers to those variables that will be used the most in a given time period．This approach requires the use of sophisticated programanalysis algorithms．The hardware approach is simply to use more registers so that more variables can be held in registers for longer periods of time． |
